Semiconductor manufacturers perform a series of tests to detect faults in manufactured ICs. Some of the defects, such as line resistive vias and bridges, can be effectively caught by conducting testing at the functional speed of the IC. Automatic Test Pattern Generation (ATPG) tools can provide fault models that can be used to generate tests for detecting at-speed failures. An ATPG tool is often used to generate a test pattern (an input or test sequence) that, when applied to an IC, allows a tester to determine between correct circuit behavior and faulty circuit behavior caused by defects.
The generated test patterns for at-speed testing require a first part that launches a logic transition value along a path and a second part that captures the response at a particular time based on the clock speed of the system. In a typical synchronous design style, the logic transition value is applied (“launched”) at a launch flip-flop of the path and retrieved (“captured”) at a capture flip-flop of the path. Located between the launch flip-flop and the capture flip-flop of the path is combinational logic.
Inline resistive fault (IRF) pattern generation is an example of a test pattern generated for at-speed testing of an IC. IRF pattern generation is used to create at-speed scan based testing patterns to launch data from one register (i.e., the launch flip-flop) and capture the data at the next register (i.e., the capture flip-flop) while operating the IC at or close to the functional speed. IRF patterns test one polarity of data transitioning through the path so at the capture register (or capture flip-flop) data will either be rising or falling, but both directions are not tested.
Due to the manner in which storage elements are characterized in a cell library, IRF patterns may be generated that allow setup times to be missed and the capture flip-flop still capture data. Setup time is understood as the amount of time needed for an input data signal to precede the arrival of the clock signal at a clocked element and result in a known clock to output delay value. Setup time is not a timing requirement for a storage element to successfully capture arriving data. A storage element may still capture data when the setup time is missed, but the magnitude of the setup time miss can vary greatly between if rising or falling data is arriving at the storage element. Since data may still be captured even when setup times are missed, the results of IRF testing may be flawed. As such, improved IRF testing would be beneficial in the art.